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面向集成电路电阻电容提取的高级场求解器技术电子书

电阻、电容(RC)提取是设计纳米制造工艺集成电路的重要步骤,通过它对集成电路中的互连线或衬底耦合效应进行电学建模,为进一步的电路性能验证、制造良率分析提供基础。

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作       者:喻文健,王习仁

出  版  社:清华大学出版社

出版时间:2014-05-01

字       数:6604

所属分类: 科技 > 工业技术 > 航空/电子

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电阻、电容(RC)提取是设计纳米制造工艺集成电路的重要步骤,通过它对集成电路中的互连线或衬底耦合效应行电学建模,为一步的电路性能验证、制造良率分析提供基础。用于RC提取的场求解器方法直对电场行求解,因此具有的准确度。为了满足集成电路设计中准确建模与仿真的要求,场求解器RC提取方法正变得越来越重要。本书对刻画超大规模集成电路互连线和混合信号集成电路衬底耦合效应的关键场求解器提取方法行了全面、系统的介绍。通过来自实际电路设计的例子,对各种场求解器算法行了详细阐述,并说明它们各自的优和缺。 本书适合于电子工程和计算机工程相关专业的研究生和学者阅读,也可为工作在集成电路设计、设计自动化领域的技术人员提供参考。<br/>
目录展开

扉页

内容简介

版权页

Foreword

Preface

Acknowledgment

Content

Chapter1 Introduction

1.1 The Need for Parasitic Extraction

1.2 The Methods for RC Extraction and Field Solver

1.3 Book Outline

1.4 Summary

Chapter2 Basic Field-Solver Techniques for RC Extraction

2.1 Problem Formulation

2.2 Overview of the Numerical Methods

2.3 Indirect Boundary Element Method

2.4 Direct Boundary Element Method

2.5 Floating Random Walk Method

2.6 Summary

Chapter3 Fast Boundary Element Methods for CapacitanceExtraction (Ⅰ)

3.1 Basics of Indirect Boundary Element Methods

3.2 Fast Multipole Methods

3.2.1 Introduction

3.2.2 Multipole Expansions

3.2.3 Local Expansions

3.2.4 Fast Multipole Algorithm

3.3 Low-Rank Matrix Compression-Based Fast Iterative Solvers

3.3.1 Why Compression?

3.3.2 Matrix Compression Can Reduce the Complexity to Linear

3.3.3 Compression Possible?

3.3.4 Basics of Matrix Compression Using SVD and QR

3.3.5 Compression Without Building Entire Matrix Beforehand

3.4 Matrix Compression by Adaptive Cross Approximation

3.4.1 Adaptive Cross Approximation (ACA)

3.4.2 Recompression of Adaptive Cross Approximation

3.5 Summary

Chapter4 Fast Boundary Element Methods for Capacitance Extraction (Ⅱ)

4.1 Direct Boundary Element Method for Multi-dielectric Capacitance Extraction

4.2 The Quasi-multiple Medium Approach

4.2.1 Basic Idea

4.2.2 Decomposition of Dielectrics and Boundary Element Partition

4.2.3 Algorithm Description and Analysis

4.3 Equation Organization and Solving Techniques

4.3.1 Organization of the Coefficient Matrix

4.3.2 Extended Jacobi and MN Preconditioners

4.4 Numerical Results

4.4.1 The Comparison with GIMEI

4.4.2 The Comparison with ODDM

4.4.3 The Results for Structures from Real Design

4.4.4 The Comparison with FastCap

4.5 Efficient Techniques for Handling Floating Metal Fills

4.5.1 Basic Idea

4.5.2 Equation Formation and Solution

4.5.3 Numerical Results

4.6 Summary

Chapter5 Resistance Extraction of Complex 3-D Interconnects

5.1 Analytical Resistance Formulation

5.2 Field Solver for Interconnect Resistance

5.2.1 Resistance Network of Multiterminal Regions

5.2.2 Resistance Calculation Using Direct BEM

5.3 Fast BEM Solver Using Linear Boundary Elements

5.3.1 Physics-Based Nonuniform Virtual Cutting

5.3.2 Discarding Conductors Not in the Path of Direct Current

5.3.3 Dividing Elements Only in One Direction When Possible

5.3.4 Linear Boundary Elements for Straight Conductors

5.3.5 Efficiency Summary

5.4 Analytical QBEM Extraction

5.4.1 General Analytical QBEM Algorithm

5.4.2 Distinguish Between Regular and Irregular Subregions

5.4.3 Compute the Resistance Network of the Whole Region

5.4.4 Numerical Result and Analysis

5.5 Summary

Appendix 5.A

Chapter6 Substrate Resistance Extraction with Boundary Element Method

6.1 Field Solver for Substrate Resistance

6.2 Efficient Field-Solver Techniques

6.2.1 NonuniformMeshing

6.2.2 Numerical Reduction of Linear Equation System

6.2.3 Quasi-multiple Medium Technique to Sparsify Matrix

6.3 Numerical Experiments

6.3.1 Simple One-Layer Substrate

6.3.2 The 52-Contact Structure with Three Doping Profiles

6.3.3 Test Structure with Lateral Resistivity Variation

6.4 Summary

Chapter7 Extracting Frequency-Dependent Substrate Parasitics

7.1 Field Solver for Substrate Capacitance and Resistance

7.2 Direct Boundary Element Method for Substrate Impedance Extraction

7.3 The Two-Step Approach

7.3.1 Frequency-Dependent Entries in Matrix A

7.3.2 Perturbed Equation System and Its Efficient Solution

7.4 Efficient Technique for Solving the Real-Valued System

7.5 Overall Algorithm Flow and Discussion

7.6 Numerical Results

7.6.1 Substrate with 52 Contacts

7.6.2 More Numerical Experiments

7.7 Summary

Chapter8 Process Variation-Aware Capacitance Extraction

8.1 Motivation

8.2 The Incremental BEM for Variation-Aware Capacitance Library Building

8.2.1 Basic Idea

8.2.2 Modification of the Coefficient Matrix and the Solving Technique

8.2.3 Numerical Results

8.3 Preliminaries of Variation-Aware Statistical Capacitance Extraction

8.3.1 Grid-Based Process Variation Model

8.3.2 The Hermite Polynomial Collocation Method

8.4 Chip-Level Statistical Capacitance Extraction Considering Spatial Correlation

8.4.1 Intra-window Capacitance Extraction with the Grid-Based Variation Model

8.4.2 Calculation of Inter-window Capacitance Covariance

8.4.3 Complexity Analysis of the Inter-window Calculation

8.4.4 Statistical Model of Full-Path Capacitance

8.5 Experiments of Statistical Capacitance Extraction

8.5.1 Simple Cases with Parallel-Line Structure

8.5.2 A Large Case with Multilayered Structure

8.6 Summary

Appendix 8.A.Complete Proof of Theorem 8.3

Chapter9 Statistical Capacitance Extraction Based on Continuous-Surface Geometric Model

9.1 The Continuous-Surface Model for Geometric Variation

9.1.1 Three Geometric Variation Models

9.1.2 The Reasonable CSV Model for On-Chip Interconnect

9.1.3 The Comparison of Three Geometric Variation Models

9.2 Efficient Statistical Extraction Techniques

9.2.1 The Weighted PFA for Variable Reduction

9.2.2 Parallel Statistical Capacitance Extraction

9.2.3 Calculating the Inter-window Covariance of Capacitance

9.3 Fast Approaches to Model the Line-Edge Roughness

9.3.1 Background

9.3.2 The Adjoint Field Technique for Sensitivity Calculation

9.3.3 Two Efficient Approaches

9.3.4 Numerical Results

9.3.5 More Analysis Results and Discussion

9.4 Summary

Chapter10 Fast Floating Random Walk Method for Capacitance Extraction

10.1 The Basic Floating Random Walk Algorithms

10.1.1 Numerical Technique to Calculate Multi-dielectricSurface Green's Function

10.2 A Multi-dielectric FRW Algorithm with the Precharacterized Probabilities and Weight Values

10.2.1 The Basic Idea

10.2.2 The Details of the Precharacterization Procedure

10.2.3 The FRW Algorithm with Multi-dielectric GFTs and WVTs

10.3 The Techniques for Variance Reduction

10.3.1 Background

10.3.2 The Importance Sampling with the Weight Values Averaged

10.3.3 The Comprehensive Variance Reduction Scheme

10.4 The Space Management Technique and Parallel Implementation

10.4.1 The Space Management Technique

10.4.2 The Parallel Implementation

10.5 Numerical Results

10.5.1 Test Cases

10.5.2 Validating the Multi-dielectric FRW Algorithm

10.5.3 Validating the Variance Reduction Techniques

10.5.4 Comparing with the Fast Boundary Element Method

10.5.5 Validating the Efficiency of Parallel Computing

10.6 Summary

Chapter11 FRW-Based Solver for Chip-Scale Large Structures

11.1 Motivation

11.2 Basic Operations of Space Management and Accelerating Techniques

11.2.1 Basic Operations

11.2.2 Improving the Candidate Checking with Distance Limit

11.2.3 Incomplete Candidate List

11.2.4 Reducing the Time for Inquiring the Candidate List

11.3 Space Management Structures and Approaches

11.3.1 The Improved Octree-Based Approach

11.3.2 Two Grid-Based Approaches

11.3.3 The Hybrid Approach Using Grid and Octree

11.4 Numerical Results

11.4.1 Test Cases

11.4.2 Validating the Three Accelerating Techniques

11.4.3 Evaluating Different Space Management Approaches

11.4.4 RWCap2 with the Hybrid Approach Using Grid and Octree

11.4.5 The Results for Multi-dielectric Cases

11.5 Summary

References

Index

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